1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to the apparatus for executing the floating point operations of a data processing system.
2. Description of the Related Art
Data processing systems are typically provided with the capability of manipulating numerical quantities stored in the floating point format. In the floating point format, a numerical quantity is represented by a fraction value and by an (exponent) argument value. The argument value represents the power to which the exponent base is raised, while the fraction value represents the number multiplying exponential portion of the number. The principal advantage of the floating point format is the increased range of numbers that can be manipulated in the data processing systems without instituting extraordinary procedures or conventions. A floating point processor capable of advantageously using the invention disclosed herein is described in "The MicroVAX 78132 Floating Point Chip" by William R. Bidermann, Amnon Fisher, Burton M. Leary, Robert J. Simcoe and William R. Wheeler, Digital Technical Journal, No. 2, March, 1986, pages 24-36.
The floating point format has the disadvantage that the execution of addition and subtraction operations in this data format is more complex and requires a greater time period than the same operation in the standard data format. This complexity if the result of having to align fractions prior to their addition or subtraction so that the exponents are identical, and then potentially having to normalize the result, i.e., shifting the fraction of the resulting quantity until a logic "1" is stored in the most significant bit position and adjusting the argument of the exponent accordingly.
Referring now to FIG. 1, the addition and subtraction operations are defined in terms of effective addition and effective subtraction operations which more correctly identify related operation sequences. The addition and subtraction operations 101 are grouped into an effective addition operation 102 and an effective subtraction operation 103. The effective addition operation 102 includes the operations of adding operands that have the same sign and subtracting operands that have different signs. The effective subtraction operation 103 includes the addition of operands with differing signs and the subtraction of operands with the same sign.
Referring next to FIG. 2, the steps in performing the effective subtract operation, according to the related art, is shown. In step 201, the difference between the exponents is determined. Based on the difference between exponents, the logic signals representing the smaller operands are shifted until the arguments of the exponents representing the two operands are the same, i.e., the operand fractions are aligned, in step 202. In step 203, the aligned quantities are then subtracted. If the resulting quantity is negative, then the 2's complement must be calculated, i.e., the subtrahend was larger than the minuend in step 204. In step 205, the most significant non-zero bit position (i.e., the leading logic "1" signal) is determined. Based on this bit position, the resulting quantity operand, is normalized, the leading logic "1" signal is shifted to the most significant bit position and the argument of the exponent is adjusted accordingly in step 206. In step 207, the rounding of the resulting operand fraction is performed. As will be clear to those familiar with the implementation of floating point operations, the seven steps of the effective subtraction operation of FIG. 2 can require a relatively long time for their execution.
A need has therefore been felt for a procedure and associated apparatus for accelerating the effective subtraction operation.